Low power correlator of DSP core for communication system

Ya Lan Tsao*, Jun Xian Teng, Maw Ching Lin, Shyh-Jye Jou

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    摘要

    Correlator is the most demanded block in communication systems. In this paper, low power correlator block is implemented into an embedded DSP core as a special block. This special block of correlator can employ data bus bandwidth of DSP efficiently. The design results show that it use only 3235 gate counts and can reduce the correlation operations from 20 instructions (without correlator) to only 4 instructions.

    原文English
    頁面217-220
    頁數4
    DOIs
    出版狀態Published - 12月 2004
    事件2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, 台灣
    持續時間: 6 12月 20049 12月 2004

    Conference

    Conference2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
    國家/地區台灣
    城市Tainan
    期間6/12/049/12/04

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