Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

Chang Tzu Wang; Ming-Dou Ker; Tien Hao Tang; Kuan Cheng Su

doi:10.1109/ICICDT.2009.5166256

Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

Chang Tzu Wang^*, Ming-Dou Ker, Tien Hao Tang, Kuan Cheng Su

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

摘要

A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit, composed of the SCR device and new ESD detection circuit, has been designed with consideration of gate current to reduce the total standby leakage current under normal circuit operating conditions. After fabrication in a 1-V 65-nm fully-silicided CMOS process, the proposed power-rail ESD clamp circuit can sustain 7kV human-body-model (HBM) and 325V machine model (MM) ESD tests which occupying an silicon area of only 49μmx21μm and consuming a very low standby leakage current of 96nA at room temperature.

原文	English
主出版物標題	2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009
頁面	21-24
頁數	4
DOIs	https://doi.org/10.1109/ICICDT.2009.5166256
出版狀態	Published - 1 12月 2009
事件	2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 - Austin, TX, United States 持續時間: 18 5月 2009 → 20 5月 2009

出版系列

名字	2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

Conference

Conference	2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009
國家/地區	United States
城市	Austin, TX
期間	18/05/09 → 20/05/09

存取文件

10.1109/ICICDT.2009.5166256

其它文件與鏈接

Link to publication in Scopus

引用此

Wang, C. T., Ker, M.-D., Tang, T. H., & Su, K. C. (2009). Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology. 於 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 (頁 21-24). 文章 5166256 (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009). https://doi.org/10.1109/ICICDT.2009.5166256

@inproceedings{14060e59360f4dba8c212dded99b035c,

title = "Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology",

abstract = "A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit, composed of the SCR device and new ESD detection circuit, has been designed with consideration of gate current to reduce the total standby leakage current under normal circuit operating conditions. After fabrication in a 1-V 65-nm fully-silicided CMOS process, the proposed power-rail ESD clamp circuit can sustain 7kV human-body-model (HBM) and 325V machine model (MM) ESD tests which occupying an silicon area of only 49μmx21μm and consuming a very low standby leakage current of 96nA at room temperature.",

keywords = "Electrostatic discharge (ESD), Gate leakage, Power-rail ESD clamp circuit, Silicon controlled rectifier (SCR)",

author = "Wang, {Chang Tzu} and Ming-Dou Ker and Tang, {Tien Hao} and Su, {Kuan Cheng}",

year = "2009",

month = dec,

day = "1",

doi = "10.1109/ICICDT.2009.5166256",

language = "English",

isbn = "9781424429332",

series = "2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009",

pages = "21--24",

booktitle = "2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009",

note = "2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 ; Conference date: 18-05-2009 Through 20-05-2009",

}

Wang, CT, Ker, M-D, Tang, TH & Su, KC 2009, Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology. 於 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009., 5166256, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009, 頁 21-24, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009, Austin, TX, United States, 18/05/09. https://doi.org/10.1109/ICICDT.2009.5166256

Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology. / Wang, Chang Tzu; Ker, Ming-Dou; Tang, Tien Hao 等.
2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. 2009. p. 21-24 5166256 (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

AU - Wang, Chang Tzu

AU - Ker, Ming-Dou

AU - Tang, Tien Hao

AU - Su, Kuan Cheng

PY - 2009/12/1

Y1 - 2009/12/1

N2 - A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit, composed of the SCR device and new ESD detection circuit, has been designed with consideration of gate current to reduce the total standby leakage current under normal circuit operating conditions. After fabrication in a 1-V 65-nm fully-silicided CMOS process, the proposed power-rail ESD clamp circuit can sustain 7kV human-body-model (HBM) and 325V machine model (MM) ESD tests which occupying an silicon area of only 49μmx21μm and consuming a very low standby leakage current of 96nA at room temperature.

AB - A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit, composed of the SCR device and new ESD detection circuit, has been designed with consideration of gate current to reduce the total standby leakage current under normal circuit operating conditions. After fabrication in a 1-V 65-nm fully-silicided CMOS process, the proposed power-rail ESD clamp circuit can sustain 7kV human-body-model (HBM) and 325V machine model (MM) ESD tests which occupying an silicon area of only 49μmx21μm and consuming a very low standby leakage current of 96nA at room temperature.

KW - Electrostatic discharge (ESD)

KW - Gate leakage

KW - Power-rail ESD clamp circuit

KW - Silicon controlled rectifier (SCR)

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U2 - 10.1109/ICICDT.2009.5166256

DO - 10.1109/ICICDT.2009.5166256

M3 - Conference contribution

AN - SCOPUS:77950333975

SN - 9781424429332

T3 - 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

SP - 21

EP - 24

BT - 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

T2 - 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

Y2 - 18 May 2009 through 20 May 2009

ER -

Wang CT, Ker MD, Tang TH, Su KC. Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology. 於 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. 2009. p. 21-24. 5166256. (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009). doi: 10.1109/ICICDT.2009.5166256

Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

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Conference

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