Low-Error Reduced-Width Booth Multipliers for DSP Applications

Keyphrases

• Booth multiplier 100%
• C Code 20%
• Compensation Amount 20%
• Compensation Vector 40%
• Critical Path Delay 40%
• DSP Applications 100%
• Filtering System 20%
• Gate Count 20%
• Hardware Reduction 20%
• Low Error 100%
• Proposed Architecture 20%
• Pulse Shaping Filter 20%
• Reduced Height 100%
• System Application 20%
• Transceiver 20%
• Truncation 20%
• Verilog Code 20%

Engineering

• Critical Path 100%
• Design Result 50%
• Filter System 50%
• Input Data 100%
• Pulse Shaping 50%
• Shaping Filter 50%
• Transceiver 50%
• Truncation 50%