Low-Error Reduced-Width Booth Multipliers for DSP Applications

Shyh-Jye Jou*, Meng Hung Tsai, Ya Lan Tsao

*此作品的通信作者

研究成果: Article同行評審

60 引文 斯高帕斯(Scopus)

摘要

A low-error reduced-width Booth multiplier using a proper compensation vector is proposed. The compensation vector is dependent on the input data. The compensation value will thus be adaptively adjusted when the input data are different. Design results from a 16 × 16 to 16 Booth multiplier show that the gate counts and critical path delay of the new reduced-width multipliers is 50.94% and 66.04% of the post-truncation reduced-width multiplier. A module generator of our proposed architecture is developed that will generate C code and Verilog code for each reduced-width multiplier. Pulse-shaping filter-system applications used in CATV transceivers show promising performance with 50.04% hardware reduction and 33.82% reduction in the critical path delay.

原文English
頁(從 - 到)1470-1474
頁數5
期刊IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
50
發行號11
DOIs
出版狀態Published - 11月 2003

指紋

深入研究「Low-Error Reduced-Width Booth Multipliers for DSP Applications」主題。共同形成了獨特的指紋。

引用此