Low Dit high-k/In0.53Ga0.47As gate stack, with CET down to 0.73 nm and thermally stable silicide contact by suppression of interfacial reaction

D. Hassan Zadeh, H. Oomine, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K. Tsutsui, K. Natori, H. Iwai

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

Ultra-thin InGaAs gate stacks with CET= 0.73 nm (EOT< 0.5 nm), D it as low as 8.0×1011 (cm-2 eV -1) and thermal stability up to 600°C is demonstrated by using La2O3 as gate dielectric. A silicide/InGaAs junction with excellent controllability at the interface is also proposed. These results promise the integration compatibility of this gate stack for future node 3D device structures.

原文English
主出版物標題2013 IEEE International Electron Devices Meeting, IEDM 2013
頁面2.4.1-2.4.4
DOIs
出版狀態Published - 2013
事件2013 IEEE International Electron Devices Meeting, IEDM 2013 - Washington, DC, United States
持續時間: 9 十二月 201311 十二月 2013

出版系列

名字Technical Digest - International Electron Devices Meeting, IEDM
ISSN(列印)0163-1918

Conference

Conference2013 IEEE International Electron Devices Meeting, IEDM 2013
國家/地區United States
城市Washington, DC
期間9/12/1311/12/13

指紋

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