Low-cost architecture design with efficient data arrangement and memory configuration for MPEG-2 audio decoder

Tsung Han Tsai*, Liang Gee Chen, Sheng-Chieh Huang, Hao Chieh Chang

*此作品的通信作者

研究成果: Conference article同行評審

1 引文 斯高帕斯(Scopus)

摘要

The paper describes a low-cost MPEG-2 audio decoder with a modified fast algorithm for decoding. In the modified decoding scheme, the computation amount of the bottleneck module can be reduced into one-fourths of the original one. Also, the major memory storage only requires half size of the standard synthesis subband filterbank. The decoder is developed for the approaches of simplicity and low-cost architecture design, with the techniques of intelligent data arrangement and memory configuration.

原文English
頁(從 - 到)65-68
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
4
DOIs
出版狀態Published - 1 1月 1998
事件Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA
持續時間: 31 5月 19983 6月 1998

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