@inproceedings{d6e879baf81541b294ae4fd1d417f80c,
title = "Low-Complexity Pseudo Direct Learning Digital Pre-Distortion Architecture for Nonlinearity and Memory Effect of Power Amplifier in mmWave Baseband Transmitter",
abstract = "In this paper, we design a power amplifier (PA) digital pre-distortion (DPD) module at the baseband transmitter to pre-compensate the nonlinearity and memory effect of the PA. In terms of DPD, we propose a low-complexity pseudo direct learning (PDL) DPD architecture based on the system level point of view according to the IEEE 802.11ad/ay specifications. The compensated error vector magnitude (EVM) performance of nonlinearity and memory effects can be improved from-12.8 dB to-21.7 dB at 16-QAM mode. The gain flatness of the-3 dB bandwidth can be extended from 0.3pi to 0.78pi with improving of 2.6 times. For the hardware implementation, we use TSMC 28-nm HPC_PLUS CMOS technology with four times parallelism to achieve 2.5 GHz chip rate. The gate counts and power of the proposed DPD design are 273.1 K and 98.0 mW, respectively.",
keywords = "digital pre-distortion, error vector magnitude, power amplifier, pseudo direct learning",
author = "Lu, {Shen Zhe} and Xue, {Nai Cheng} and Liu, {Hung Chih} and Chih-Wei Jen and Jou, {Shyh Jye}",
note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022 ; Conference date: 27-05-2022 Through 01-06-2022",
year = "2022",
doi = "10.1109/ISCAS48785.2022.9937637",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1541--1545",
booktitle = "IEEE International Symposium on Circuits and Systems, ISCAS 2022",
address = "United States",
}