Low-Complexity Pseudo Direct Learning Digital Pre-Distortion Architecture for Nonlinearity and Memory Effect of Power Amplifier in mmWave Baseband Transmitter

Shen Zhe Lu, Nai Cheng Xue, Hung Chih Liu, Chih-Wei Jen, Shyh Jye Jou

研究成果: Conference contribution同行評審

摘要

In this paper, we design a power amplifier (PA) digital pre-distortion (DPD) module at the baseband transmitter to pre-compensate the nonlinearity and memory effect of the PA. In terms of DPD, we propose a low-complexity pseudo direct learning (PDL) DPD architecture based on the system level point of view according to the IEEE 802.11ad/ay specifications. The compensated error vector magnitude (EVM) performance of nonlinearity and memory effects can be improved from-12.8 dB to-21.7 dB at 16-QAM mode. The gain flatness of the-3 dB bandwidth can be extended from 0.3pi to 0.78pi with improving of 2.6 times. For the hardware implementation, we use TSMC 28-nm HPC_PLUS CMOS technology with four times parallelism to achieve 2.5 GHz chip rate. The gate counts and power of the proposed DPD design are 273.1 K and 98.0 mW, respectively.

原文English
主出版物標題IEEE International Symposium on Circuits and Systems, ISCAS 2022
發行者Institute of Electrical and Electronics Engineers Inc.
頁面1541-1545
頁數5
ISBN(電子)9781665484855
DOIs
出版狀態Published - 2022
事件2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022 - Austin, United States
持續時間: 27 5月 20221 6月 2022

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
2022-May
ISSN(列印)0271-4310

Conference

Conference2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022
國家/地區United States
城市Austin
期間27/05/221/06/22

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