Logic/resistive-switching hybrid transistor for two-bit-per-cell storage

Shih Chieh Wu; Chieh Lo; Tuo-Hung Hou

doi:10.1109/VLSI-TSA.2012.6210103

Logic/resistive-switching hybrid transistor for two-bit-per-cell storage

Shih Chieh Wu, Chieh Lo, Tuo-Hung Hou^*

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

摘要

Various bias schemes in the RS-TFT have been comprehensively investigated. As shown in Table I, the V _D -biased bipolar RS is superior for the logic/RS hybrid operation with the ability of two-bit-per-cell storage because of its large program margin, localized filament location, negligible V _TH shift, and suppressed gate leakage current. In comparison with other embedded memory technologies, the proposed RS-TFT in this work not only is compatible with logic CMOS technology, but also provides comparable memory performance with a very competitive cell size.

原文	English
主出版物標題	2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012 - Proceedings of Technical Papers
DOIs	https://doi.org/10.1109/VLSI-TSA.2012.6210103
出版狀態	Published - 16 7月 2012
事件	2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012 - Hsinchu, Taiwan 持續時間: 23 4月 2012 → 25 4月 2012

出版系列

名字	International Symposium on VLSI Technology, Systems, and Applications, Proceedings
ISSN（列印）	1930-8868

Conference

Conference	2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012
國家/地區	Taiwan
城市	Hsinchu
期間	23/04/12 → 25/04/12

存取文件

10.1109/VLSI-TSA.2012.6210103

其它文件與鏈接

Link to publication in Scopus

引用此

Wu, S. C., Lo, C., & Hou, T-H. (2012). Logic/resistive-switching hybrid transistor for two-bit-per-cell storage. 於 2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012 - Proceedings of Technical Papers [6210103] (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). https://doi.org/10.1109/VLSI-TSA.2012.6210103

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abstract = " Various bias schemes in the RS-TFT have been comprehensively investigated. As shown in Table I, the V D -biased bipolar RS is superior for the logic/RS hybrid operation with the ability of two-bit-per-cell storage because of its large program margin, localized filament location, negligible V TH shift, and suppressed gate leakage current. In comparison with other embedded memory technologies, the proposed RS-TFT in this work not only is compatible with logic CMOS technology, but also provides comparable memory performance with a very competitive cell size.",

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Wu, SC, Lo, C & Hou, T-H 2012, Logic/resistive-switching hybrid transistor for two-bit-per-cell storage. 於 2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012 - Proceedings of Technical Papers., 6210103, International Symposium on VLSI Technology, Systems, and Applications, Proceedings, 2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012, Hsinchu, Taiwan, 23/04/12. https://doi.org/10.1109/VLSI-TSA.2012.6210103

Logic/resistive-switching hybrid transistor for two-bit-per-cell storage. / Wu, Shih Chieh; Lo, Chieh; Hou, Tuo-Hung.

2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012 - Proceedings of Technical Papers. 2012. 6210103 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

研究成果: Conference contribution › 同行評審

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AU - Lo, Chieh

AU - Hou, Tuo-Hung

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N2 - Various bias schemes in the RS-TFT have been comprehensively investigated. As shown in Table I, the V D -biased bipolar RS is superior for the logic/RS hybrid operation with the ability of two-bit-per-cell storage because of its large program margin, localized filament location, negligible V TH shift, and suppressed gate leakage current. In comparison with other embedded memory technologies, the proposed RS-TFT in this work not only is compatible with logic CMOS technology, but also provides comparable memory performance with a very competitive cell size.

AB - Various bias schemes in the RS-TFT have been comprehensively investigated. As shown in Table I, the V D -biased bipolar RS is superior for the logic/RS hybrid operation with the ability of two-bit-per-cell storage because of its large program margin, localized filament location, negligible V TH shift, and suppressed gate leakage current. In comparison with other embedded memory technologies, the proposed RS-TFT in this work not only is compatible with logic CMOS technology, but also provides comparable memory performance with a very competitive cell size.

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SN - 9781457720840

T3 - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

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Y2 - 23 April 2012 through 25 April 2012

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Logic/resistive-switching hybrid transistor for two-bit-per-cell storage

摘要

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Conference

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