Logic and fault simulation by cellular automata

Yih-Lang Li*, Cheng Wen Wu

*此作品的通信作者

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

We propose a massively parallel architecture to speed up the logic and fault simulation. We use a 2-D cellular automata (CA) to implement the logic and fault simulation of combinational circuits. Our CA has six cell states, and operates in a pipelined fashion. Experimental results on ISCAS85 benchmark circuits show that our CA outperforms the previously reported parallel simulators. As to pure logic simulation, our CA performs up to 9.24 billion GEPS using a 20 MHz clock and 8-bit words as opposed to 5 billion GEPS.

原文English
主出版物標題Proceedings of the European Design and Test Conference
編輯 Anon
發行者Publ by IEEE
頁面552-556
頁數5
ISBN(列印)0818654112
DOIs
出版狀態Published - 1 1月 1994
事件Proceedings of the European Design and Test Conference - Paris, Fr
持續時間: 28 2月 19943 3月 1994

出版系列

名字Proceedings of the European Design and Test Conference

Conference

ConferenceProceedings of the European Design and Test Conference
城市Paris, Fr
期間28/02/943/03/94

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