Level shifters for high-speed 1-V to 3.3-V interfaces in a 0.13-μm Cu-interconnection/low-k CMOS technology

W. T. Wang*, Ming-Dou Ker, M. C. Chiang, C. H. Chen

*此作品的通信作者

    研究成果: Paper同行評審

    40 引文 斯高帕斯(Scopus)

    摘要

    Level shifters for 1.0-V to 3.3-V high-speed interfaces are proposed. Level-up shifter uses zero-Vt 3.3-V NMOSs as voltage clamps to protect 1.0-V NMOS switches from high voltage stress across the gate oxide. Level-down shifter uses 3.3-V NMOSs as both pull-up and pull-down devices with supply voltage of 1.0-V and gate voltage swing from 0-V to 3.3-V. The zero-Vt NMOS is a standard MOSFET device in a 0.13-μm CMOS process without adding extra mask or process step to realize it. Level-up transition from 0.9-V to 3.6-V takes only 1 ns in time, and the level-down transition has no minimum core voltage limitation. These circuits do not consume static DC power, therefore they are very suitable for low-power and high-speed interfaces in the deep sub-quarter-micron CMOS technologies.

    原文English
    頁面307-310
    頁數4
    DOIs
    出版狀態Published - 26 9月 2001
    事件2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings - Hsinchu, Taiwan
    持續時間: 18 4月 200120 4月 2001

    Conference

    Conference2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings
    國家/地區Taiwan
    城市Hsinchu
    期間18/04/0120/04/01

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