Learning Based Placement Refinement to Reduce DRC Short Violations

Ying Yao Huang, Chang Tzu Lin, Wei Lun Liang, Hung Ming Chen

研究成果: Conference contribution同行評審

摘要

With the increasing complexity of the design rules, the routability has become one of the most essential factors that should be considered in the placement stage; however, being the routable basis of the placer in the past, the congestion map given by global routing cannot display the trend of routabiliy nowadays. If we want more comprehensive and close to the actual routing information, we must execute the complete flow including global routing and detailed routing, which is time-consuming. Therefore, how to access the accurate routing information rapidly is an important issue. This paper proposes a machine learning method and put it into our placement flow to help us solve the above problem. In this machine learning model, the features contain the information of placement itself and the global routing congestion. We utilize the model to predict the position of the detailed routing violations and feed the information back to placement system, and generate a new placement result afterwards. Experimental results show that comparing with the result of the original placer, the proposed methodologies can effectively decrease the number of the DRC violations.

原文English
主出版物標題2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781665419154
DOIs
出版狀態Published - 19 四月 2021
事件2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Hsinchu, Taiwan
持續時間: 19 四月 202122 四月 2021

出版系列

名字2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings

Conference

Conference2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021
國家/地區Taiwan
城市Hsinchu
期間19/04/2122/04/21

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