TY - JOUR
T1 - Layout verification to improve ESD/latchup immunity of scaled-down CMOS cell libraries
AU - Ker, Ming-Dou
AU - Hsiao, Sue Mei
AU - Lin, Jiann Horng
PY - 1997
Y1 - 1997
N2 - Layout verification has been proposed to improve the ESD (Electrostatic Discharge) and latchup immunity of scaled-down CMOS cell libraries. By using the DRC (design rules check) and ERC (electrical rules check), the ESD/latchup sensitive layout can be found. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the cells, the ESD and latchup reliability of CMOS IC's assembled by the layout-verified cell libraries can be significantly improved.
AB - Layout verification has been proposed to improve the ESD (Electrostatic Discharge) and latchup immunity of scaled-down CMOS cell libraries. By using the DRC (design rules check) and ERC (electrical rules check), the ESD/latchup sensitive layout can be found. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the cells, the ESD and latchup reliability of CMOS IC's assembled by the layout-verified cell libraries can be significantly improved.
UR - http://www.scopus.com/inward/record.url?scp=0030655535&partnerID=8YFLogxK
U2 - 10.1109/ASIC.1997.616991
DO - 10.1109/ASIC.1997.616991
M3 - Conference article
AN - SCOPUS:0030655535
SN - 1063-0988
SP - 125
EP - 129
JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
M1 - 5774221
T2 - Proceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit
Y2 - 7 September 1997 through 10 September 1997
ER -