Layout verification for submicron CMOS cell libraries to improve ESD/latchup reliability

Ming-Dou Ker; Sue Mei Hsiao; Jiann Horng Lin

doi:10.1109/VTSA.1997.614930

Layout verification for submicron CMOS cell libraries to improve ESD/latchup reliability

Ming-Dou Ker^*, Sue Mei Hsiao, Jiann Horng Lin

^*此作品的通信作者

電子研究所

研究成果: Paper › 同行評審

摘要

Layout verification has been proposed to improve the ESD and latchup immunity of scaled-down CMOS cell libraries. By using the DRC (design rules check) and ERC (electrical rules check), the layout sensitive to the ESD or latchup events can be found. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the cells, the ESD and latchup reliability of CMOS IC's assembled by the layout-verified cell libraries can be significantly improved.

原文	English
頁面	343-347
頁數	5
DOIs	https://doi.org/10.1109/VTSA.1997.614930
出版狀態	Published - 1997
事件	Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China 持續時間: 3 6月 1997 → 5 6月 1997

Conference

Conference	Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications
城市	Taipei, China
期間	3/06/97 → 5/06/97

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10.1109/VTSA.1997.614930

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abstract = "Layout verification has been proposed to improve the ESD and latchup immunity of scaled-down CMOS cell libraries. By using the DRC (design rules check) and ERC (electrical rules check), the layout sensitive to the ESD or latchup events can be found. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the cells, the ESD and latchup reliability of CMOS IC's assembled by the layout-verified cell libraries can be significantly improved.",

author = "Ming-Dou Ker and Hsiao, {Sue Mei} and Lin, {Jiann Horng}",

year = "1997",

doi = "10.1109/VTSA.1997.614930",

language = "English",

pages = "343--347",

note = "Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications ; Conference date: 03-06-1997 Through 05-06-1997",

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AU - Ker, Ming-Dou

AU - Hsiao, Sue Mei

AU - Lin, Jiann Horng

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Y1 - 1997

N2 - Layout verification has been proposed to improve the ESD and latchup immunity of scaled-down CMOS cell libraries. By using the DRC (design rules check) and ERC (electrical rules check), the layout sensitive to the ESD or latchup events can be found. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the cells, the ESD and latchup reliability of CMOS IC's assembled by the layout-verified cell libraries can be significantly improved.

AB - Layout verification has been proposed to improve the ESD and latchup immunity of scaled-down CMOS cell libraries. By using the DRC (design rules check) and ERC (electrical rules check), the layout sensitive to the ESD or latchup events can be found. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the cells, the ESD and latchup reliability of CMOS IC's assembled by the layout-verified cell libraries can be significantly improved.

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DO - 10.1109/VTSA.1997.614930

M3 - Paper

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T2 - Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications

Y2 - 3 June 1997 through 5 June 1997

ER -

Layout verification for submicron CMOS cell libraries to improve ESD/latchup reliability

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