Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits

Chih Ting Yeh; Yung Chih Liang; Ming-Dou Ker

doi:10.1109/VDAT.2010.5496734

Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits

Chih Ting Yeh^*, Yung Chih Liang, Ming-Dou Ker

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

2 引文斯高帕斯（Scopus）

摘要

The diode operated in forward-biased condition has been widely used as an effective on-chip ESD protection device at GHz RF and high-speed I/O pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes realized in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The new ESD protection diodes can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the waffle diode. Therefore, the signal degradation of GHz RF and high-speed transmission can be reduced due to smaller parasitic capacitance from the new proposed diodes.

原文	English
主出版物標題	Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
頁面	241-244
頁數	4
DOIs	https://doi.org/10.1109/VDAT.2010.5496734
出版狀態	Published - 8 11月 2010
事件	2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 - Hsin Chu, Taiwan 持續時間: 26 4月 2010 → 29 4月 2010

出版系列

名字	Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

Conference

Conference	2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
國家/地區	Taiwan
城市	Hsin Chu
期間	26/04/10 → 29/04/10

存取文件

10.1109/VDAT.2010.5496734

其它文件與鏈接

Link to publication in Scopus

引用此

Yeh, C. T., Liang, Y. C., & Ker, M.-D. (2010). Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits. 於 Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 (頁 241-244). 文章 5496734 (Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010). https://doi.org/10.1109/VDAT.2010.5496734

@inproceedings{c3e5b8ba6a8f42d1961f3a74decc6900,

title = "Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits",

abstract = "The diode operated in forward-biased condition has been widely used as an effective on-chip ESD protection device at GHz RF and high-speed I/O pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes realized in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The new ESD protection diodes can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the waffle diode. Therefore, the signal degradation of GHz RF and high-speed transmission can be reduced due to smaller parasitic capacitance from the new proposed diodes.",

author = "Yeh, {Chih Ting} and Liang, {Yung Chih} and Ming-Dou Ker",

year = "2010",

month = nov,

day = "8",

doi = "10.1109/VDAT.2010.5496734",

language = "English",

isbn = "9781424452712",

series = "Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010",

pages = "241--244",

booktitle = "Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010",

note = "2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 ; Conference date: 26-04-2010 Through 29-04-2010",

}

Yeh, CT, Liang, YC & Ker, M-D 2010, Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits. 於 Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010., 5496734, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010, 頁 241-244, 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010, Hsin Chu, Taiwan, 26/04/10. https://doi.org/10.1109/VDAT.2010.5496734

Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits. / Yeh, Chih Ting; Liang, Yung Chih; Ker, Ming-Dou.
Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010. 2010. p. 241-244 5496734 (Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits

AU - Yeh, Chih Ting

AU - Liang, Yung Chih

AU - Ker, Ming-Dou

PY - 2010/11/8

Y1 - 2010/11/8

N2 - The diode operated in forward-biased condition has been widely used as an effective on-chip ESD protection device at GHz RF and high-speed I/O pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes realized in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The new ESD protection diodes can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the waffle diode. Therefore, the signal degradation of GHz RF and high-speed transmission can be reduced due to smaller parasitic capacitance from the new proposed diodes.

AB - The diode operated in forward-biased condition has been widely used as an effective on-chip ESD protection device at GHz RF and high-speed I/O pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes realized in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The new ESD protection diodes can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the waffle diode. Therefore, the signal degradation of GHz RF and high-speed transmission can be reduced due to smaller parasitic capacitance from the new proposed diodes.

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U2 - 10.1109/VDAT.2010.5496734

DO - 10.1109/VDAT.2010.5496734

M3 - Conference contribution

AN - SCOPUS:78049362075

SN - 9781424452712

T3 - Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

SP - 241

EP - 244

BT - Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

T2 - 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

Y2 - 26 April 2010 through 29 April 2010

ER -

Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits

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