Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-μm salicided CMOS process

Keyphrases

• CMOS Process 100%
• On-chip ESD Protection 100%
• Multi-finger MOSFET 100%
• Layout Design 100%
• ESD Robustness 66%
• ESD Current 33%
• Current Distribution 33%
• Power Lines 33%
• Deep Submicron Technology 33%
• MOSFET Device 33%
• CMOS IC 33%
• Source Area 33%
• Guard Ring 33%
• O-cell 33%

Engineering

• Metal-Oxide-Semiconductor Field-Effect Transistor 100%
• Current Distribution 33%
• Power Line 33%
• Source Region 33%
• Line Connection 33%