Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-μm salicided CMOS process

Ming-Dou Ker*, Che Hao Chuang, Wen Yu Lo

*此作品的通信作者

    研究成果: Conference contribution同行評審

    18 引文 斯高帕斯(Scopus)

    摘要

    The layout design to improve uniform ESD current distribution in multi-finger MOSFET devices for better ESD robustness is investigated in a 0.18-μm salicided CMOS process. The multi-finger MOSFET, without adding the pick-up guard ring inserted into its source region, or with the vertical direction of power line connection, can sustain a higher ESD level. The layout of I/O cell can be drawn more compactly, but still to provide deep-submicron CMOS IC's with higher ESD robustness.

    原文English
    主出版物標題ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems
    頁面361-364
    頁數4
    DOIs
    出版狀態Published - 1 12月 2001
    事件8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001 - , 馬耳他
    持續時間: 2 9月 20015 9月 2001

    出版系列

    名字Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
    1

    Conference

    Conference8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001
    國家/地區馬耳他
    期間2/09/015/09/01

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