Layout design on bond pads to improve the firmness of bond wire in packaged IC products

Jeng Jie Peng; Ming-Dou Ker; Nien Ming Wang; Hsin Chin Jiang

doi:10.1109/VTSA.1999.786022

Layout design on bond pads to improve the firmness of bond wire in packaged IC products

Jeng Jie Peng^*
, Ming-Dou Ker
, Nien Ming Wang
, Hsin Chin Jiang

^*此作品的通信作者

電子研究所

研究成果: Conference article › 同行評審

2 引文斯高帕斯（Scopus）

摘要

During the manufacture of IC products, the break of bond wires or the peeling of bond pads occurs frequently and thus results in the open circuit phenomenon in the IC's. There are several methods proposed to overcome this problem, but additional special process flows are desired for all of these previous methods. This paper presents a layout design method to improve the bond wire reliability in a standard CMOS process. By changing the layout patterns on the bond pads, the firmness of bond wires on the bond pads can be improved. One set of layout patterns on the bond pads has been designed and fabricated in a 0.6μm IP3M CMOS process for the ball shear test and the wire pull test. By implementing the effective layout designs in IC products, the bond wire reliability can be obviously improved in a standard CMOS process.

原文	English
頁（從 - 到）	147-150
頁數	4
期刊	International Symposium on VLSI Technology, Systems, and Applications, Proceedings
DOIs	https://doi.org/10.1109/VTSA.1999.786022
出版狀態	Published - 1 1月 1999
事件	Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan 持續時間: 7 6月 1999 → 10 6月 1999

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10.1109/VTSA.1999.786022

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引用此

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title = "Layout design on bond pads to improve the firmness of bond wire in packaged IC products",

abstract = "During the manufacture of IC products, the break of bond wires or the peeling of bond pads occurs frequently and thus results in the open circuit phenomenon in the IC's. There are several methods proposed to overcome this problem, but additional special process flows are desired for all of these previous methods. This paper presents a layout design method to improve the bond wire reliability in a standard CMOS process. By changing the layout patterns on the bond pads, the firmness of bond wires on the bond pads can be improved. One set of layout patterns on the bond pads has been designed and fabricated in a 0.6μm IP3M CMOS process for the ball shear test and the wire pull test. By implementing the effective layout designs in IC products, the bond wire reliability can be obviously improved in a standard CMOS process.",

author = "Peng, \{Jeng Jie\} and Ming-Dou Ker and Wang, \{Nien Ming\} and Jiang, \{Hsin Chin\}",

year = "1999",

month = jan,

day = "1",

doi = "10.1109/VTSA.1999.786022",

language = "English",

pages = "147--150",

journal = "International Symposium on VLSI Technology, Systems, and Applications, Proceedings",

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note = "Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications ; Conference date: 07-06-1999 Through 10-06-1999",

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TY - JOUR

T1 - Layout design on bond pads to improve the firmness of bond wire in packaged IC products

AU - Peng, Jeng Jie

AU - Ker, Ming-Dou

AU - Wang, Nien Ming

AU - Jiang, Hsin Chin

PY - 1999/1/1

Y1 - 1999/1/1

N2 - During the manufacture of IC products, the break of bond wires or the peeling of bond pads occurs frequently and thus results in the open circuit phenomenon in the IC's. There are several methods proposed to overcome this problem, but additional special process flows are desired for all of these previous methods. This paper presents a layout design method to improve the bond wire reliability in a standard CMOS process. By changing the layout patterns on the bond pads, the firmness of bond wires on the bond pads can be improved. One set of layout patterns on the bond pads has been designed and fabricated in a 0.6μm IP3M CMOS process for the ball shear test and the wire pull test. By implementing the effective layout designs in IC products, the bond wire reliability can be obviously improved in a standard CMOS process.

AB - During the manufacture of IC products, the break of bond wires or the peeling of bond pads occurs frequently and thus results in the open circuit phenomenon in the IC's. There are several methods proposed to overcome this problem, but additional special process flows are desired for all of these previous methods. This paper presents a layout design method to improve the bond wire reliability in a standard CMOS process. By changing the layout patterns on the bond pads, the firmness of bond wires on the bond pads can be improved. One set of layout patterns on the bond pads has been designed and fabricated in a 0.6μm IP3M CMOS process for the ball shear test and the wire pull test. By implementing the effective layout designs in IC products, the bond wire reliability can be obviously improved in a standard CMOS process.

UR - https://www.scopus.com/pages/publications/0032599234

U2 - 10.1109/VTSA.1999.786022

DO - 10.1109/VTSA.1999.786022

M3 - Conference article

AN - SCOPUS:0032599234

SN - 1524-766X

SP - 147

EP - 150

JO - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

JF - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

T2 - Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications

Y2 - 7 June 1999 through 10 June 1999

ER -

Layout design on bond pads to improve the firmness of bond wire in packaged IC products

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