TY - JOUR
T1 - Layout design on bond pads to improve the firmness of bond wire in packaged IC products
AU - Peng, Jeng Jie
AU - Ker, Ming-Dou
AU - Wang, Nien Ming
AU - Jiang, Hsin Chin
PY - 1999/1/1
Y1 - 1999/1/1
N2 - During the manufacture of IC products, the break of bond wires or the peeling of bond pads occurs frequently and thus results in the open circuit phenomenon in the IC's. There are several methods proposed to overcome this problem, but additional special process flows are desired for all of these previous methods. This paper presents a layout design method to improve the bond wire reliability in a standard CMOS process. By changing the layout patterns on the bond pads, the firmness of bond wires on the bond pads can be improved. One set of layout patterns on the bond pads has been designed and fabricated in a 0.6μm IP3M CMOS process for the ball shear test and the wire pull test. By implementing the effective layout designs in IC products, the bond wire reliability can be obviously improved in a standard CMOS process.
AB - During the manufacture of IC products, the break of bond wires or the peeling of bond pads occurs frequently and thus results in the open circuit phenomenon in the IC's. There are several methods proposed to overcome this problem, but additional special process flows are desired for all of these previous methods. This paper presents a layout design method to improve the bond wire reliability in a standard CMOS process. By changing the layout patterns on the bond pads, the firmness of bond wires on the bond pads can be improved. One set of layout patterns on the bond pads has been designed and fabricated in a 0.6μm IP3M CMOS process for the ball shear test and the wire pull test. By implementing the effective layout designs in IC products, the bond wire reliability can be obviously improved in a standard CMOS process.
UR - http://www.scopus.com/inward/record.url?scp=0032599234&partnerID=8YFLogxK
U2 - 10.1109/VTSA.1999.786022
DO - 10.1109/VTSA.1999.786022
M3 - Conference article
AN - SCOPUS:0032599234
SN - 1524-766X
SP - 147
EP - 150
JO - International Symposium on VLSI Technology, Systems, and Applications, Proceedings
JF - International Symposium on VLSI Technology, Systems, and Applications, Proceedings
T2 - Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications
Y2 - 7 June 1999 through 10 June 1999
ER -