摘要
Analysis of two layout designs used in the realization of MOS continuous-time integrated filters is presented. The effect of MOS parasitic capacitances is thoroughly studied and compared in the two layout design techniques. It is found that one layout method performs well at high frequencies or high Q, at the expense of increased harmonic distortion in comparison with the other method. A tradeoff between transistor matching and sensitivity to MOS intrinsic parasitic capacitances is revealed. A set of performance graphs are developed with the ratio of parasitic to integrating capacitance, C p /C, as a parameter. These graphs are useful in the design of high performance MOS continuous-time integrated filters.
| 原文 | English |
|---|---|
| 頁面 | 300-305 |
| 頁數 | 6 |
| DOIs | |
| 出版狀態 | Published - 1 12月 1994 |
| 事件 | Proceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems - Taipei, Taiwan 持續時間: 5 12月 1994 → 8 12月 1994 |
Conference
| Conference | Proceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems |
|---|---|
| 城市 | Taipei, Taiwan |
| 期間 | 5/12/94 → 8/12/94 |