Layout-Based Dual-Cell-Aware Tests

Tse Wei Wu, Dong Zhen Lee, Kai-Chiang Wu, Yu Hao Huang, Ying Yen Chen, Po Lin Chen, Mason Chern, Jih Nung Lee, Shu Yi Kao, Chia-Tso Chao

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

Conventional fault models define their faulty behavior at the IO ports of standard cells with simple rules of fault activation and fault propagation. However, there still exist some defects inside a cell (intra-cell) or between two cells (dual-cell) that cannot be effectively detected by the test patterns of conventional fault models and hence become a source of DPPM. In order to further increase the defect coverage, many research works have been conducted to study the fault models resulting from different types of intra-cell and dual-cell defects, by SPICE-simulating each targeted defect with its equivalent circuit-level defect model. However, it was considered computationally infeasible to simulate every possible defective scenario for a cell library and obtain a complete set of cell-level fault models. In this paper, we present a new dual-cell-aware (DCA) framework based on examining the layout of two adjacent cells (i.e., a dual cell) to identify potential defects, where time-consuming RC extraction can be avoided and the runtime for SPICE simulation can be reduced. Experimental results and silicon data on a SoC product show that the proposed DCA framework can not only save runtime significantly but also maintain the promising efficacy of DCA tests for the objective of lowering DPPM.

原文English
主出版物標題2019 IEEE 37th VLSI Test Symposium, VTS 2019
發行者IEEE Computer Society
ISBN(電子)9781728111704
DOIs
出版狀態Published - 1 4月 2019
事件37th IEEE VLSI Test Symposium, VTS 2019 - Monterey, United States
持續時間: 23 4月 201925 4月 2019

出版系列

名字Proceedings of the IEEE VLSI Test Symposium
2019-April

Conference

Conference37th IEEE VLSI Test Symposium, VTS 2019
國家/地區United States
城市Monterey
期間23/04/1925/04/19

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