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Layer-aware design partitioning for vertical interconnect minimization
Ya Shih Huang
*
, Yang Hsiang Liu,
Juinn-Dar Huang
*
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引文 斯高帕斯(Scopus)
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Keyphrases
Vertical Interconnect
100%
Through Silicon via
100%
Design Partitioning
100%
3D Structure
28%
Three-dimensional Design
28%
Three-dimensional (3D)
14%
Design Performance
14%
State-of-the-art Techniques
14%
Reliability Issues
14%
Wirelength
14%
Multi-way
14%
Improved Design
14%
Existing State
14%
Partitioning Algorithms
14%
Min-cut
14%
Multiple Layers
14%
Design Technology
14%
Heterogeneous System Integration
14%
Cross-layer Connection
14%
Computer Science
through silicon vias
100%
Vertical Interconnects
100%
Dimensional Structure
28%
Experimental Result
14%
Input/Output
14%
Heterogeneous System
14%
Emerging Technology
14%
System Analysis
14%
Good Starting Point
14%
Interconnection Layer
14%
Technology Design
14%