TY - JOUR
T1 - Latency-tolerant virtual cluster architecture for VLIW DSP
AU - Hsiao, Pi Chen
AU - Lin, Tay Jyi
AU - Liu, Chih-Wei
AU - Jen, Chein Wei
PY - 2007
Y1 - 2007
N2 - This paper proposes a virtual cluster architecture, which executes multi-cluster VLIW programs with a reduced number of clusters in a time-sharing fashion. The interleaved sub-VLIWs help to hide instruction latencies significantly, and thus the proposed virtual cluster will have advantages of (1) reduced forwarding complexity in the processor datapath, (2) improved programming model for further code optimizations, and (3) supporting composite instructions without any extra functional unit. In our experiments with a 4-cluster VLIW DSP, the 28 forwarding paths inside a cluster are completely eliminated, which contributes to savings of 21.71% delay and 17.56% silicon area. Moreover, the virtual cluster has been verified to have better efficiency on its code sizes and execution times for its improved programming model for various DSP kernels.
AB - This paper proposes a virtual cluster architecture, which executes multi-cluster VLIW programs with a reduced number of clusters in a time-sharing fashion. The interleaved sub-VLIWs help to hide instruction latencies significantly, and thus the proposed virtual cluster will have advantages of (1) reduced forwarding complexity in the processor datapath, (2) improved programming model for further code optimizations, and (3) supporting composite instructions without any extra functional unit. In our experiments with a 4-cluster VLIW DSP, the 28 forwarding paths inside a cluster are completely eliminated, which contributes to savings of 21.71% delay and 17.56% silicon area. Moreover, the virtual cluster has been verified to have better efficiency on its code sizes and execution times for its improved programming model for various DSP kernels.
UR - http://www.scopus.com/inward/record.url?scp=34548825970&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2007.378438
DO - 10.1109/ISCAS.2007.378438
M3 - Conference article
AN - SCOPUS:34548825970
SN - 0271-4310
SP - 3506
EP - 3509
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
M1 - 4253436
T2 - 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007
Y2 - 27 May 2007 through 30 May 2007
ER -