Late Breaking Results: PVT-Sensitive Delay Fitting for High-Performance Computing

Ding Hao Wang*, Shuo Hung Hsu, Shu Hsiang Yang, Pei Ju Lin, Hui Ting Yang, Mark Po Hung Lin

*此作品的通信作者

研究成果: Conference contribution同行評審

摘要

Aggressively monitoring and tracking system-on-chip (SoC) performance under process/voltage/temperature (PVT) variations is essential for high-performance computing systems. This work observes that different chips of the same SoC design may have different PVT-to-delay sensitivities, which must be carefully considered for accurate chip performance tracking. A learning-based method is then proposed to fit critical path delay for different chips with different PVT-to-delay sensitivities. Experimental results based on the fabricated chip samples of a 7nm SoC have justified the effectiveness of the proposed PVT-sensitive delay fitting method. Compared with the state-of-the-art, our method can achieve excellent performance tracking accuracy when the chip performance is dominated by different critical paths under different PVT conditions.

原文English
主出版物標題2023 60th ACM/IEEE Design Automation Conference, DAC 2023
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9798350323481
DOIs
出版狀態Published - 2023
事件60th ACM/IEEE Design Automation Conference, DAC 2023 - San Francisco, United States
持續時間: 9 7月 202313 7月 2023

出版系列

名字Proceedings - Design Automation Conference
2023-July
ISSN(列印)0738-100X

Conference

Conference60th ACM/IEEE Design Automation Conference, DAC 2023
國家/地區United States
城市San Francisco
期間9/07/2313/07/23

指紋

深入研究「Late Breaking Results: PVT-Sensitive Delay Fitting for High-Performance Computing」主題。共同形成了獨特的指紋。

引用此