Late breaking results: Pole-aware analog placement considering monotonic current flow and crossing-wire minimization

Abhishek Patyal, Hung-Ming Chen, Po-Hung Lin

    研究成果: Conference contribution同行評審

    摘要

    This paper presents a new paradigm for analog placement, which further incorporates poles in addition to the considerations of symmetry-island and monotonic current flow while minimizing wire crossings. The nodes along the signal path in an analog circuit contribute to the poles, and the parasitics on these dominant poles can significantly limit the circuit performance. Although the monotonic placements introduced in the previous works can generate simpler routing topologies, the unawareness of poles, especially both dominant pole and the first non-dominant pole, and wire crossing among critical nets may result in the increase wire-load and performance degradation. Experimental results show that the proposed pole-aware analog placement method considering symmetry-island, monotonic current flow, and crossing-wire minimization results in much better solution quality in terms of circuit performance.

    原文English
    主出版物標題2020 57th ACM/IEEE Design Automation Conference, DAC 2020
    發行者Institute of Electrical and Electronics Engineers Inc.
    ISBN(電子)9781450367257
    DOIs
    出版狀態Published - 七月 2020
    事件57th ACM/IEEE Design Automation Conference, DAC 2020 - Virtual, San Francisco, United States
    持續時間: 20 七月 202024 七月 2020

    出版系列

    名字Proceedings - Design Automation Conference
    2020-July
    ISSN(列印)0738-100X

    Conference

    Conference57th ACM/IEEE Design Automation Conference, DAC 2020
    國家/地區United States
    城市Virtual, San Francisco
    期間20/07/2024/07/20

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