Latchup in bulk FinFET technology

C. T. Dai, S. H. Chen, D. Linten, M. Scholz, G. Hellings, R. Boschke, J. Karp, M. Hart, G. Groeseneken, Ming-Dou Ker, A. Mocuta, N. Horiguchi

研究成果: Conference contribution同行評審

15 引文 斯高帕斯(Scopus)

摘要

Latchup (LU) had been considered to be less important in advanced CMOS technologies. However, I/O interface and analog applications can still operate at high voltage (e.g., 1.8V or 3.3V) in sub-20nm bulk FinFET technologies. LU threats are never eliminated and the sensitivity towards LU is increased in bulk FinFET technology.

原文English
主出版物標題2017 International Reliability Physics Symposium, IRPS 2017
發行者Institute of Electrical and Electronics Engineers Inc.
頁面EL1.1-EL1.3
ISBN(電子)9781509066407
DOIs
出版狀態Published - 30 5月 2017
事件2017 International Reliability Physics Symposium, IRPS 2017 - Monterey, United States
持續時間: 2 4月 20176 4月 2017

出版系列

名字IEEE International Reliability Physics Symposium Proceedings
ISSN(列印)1541-7026

Conference

Conference2017 International Reliability Physics Symposium, IRPS 2017
國家/地區United States
城市Monterey
期間2/04/176/04/17

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