LATCHUP-FREE CMOS STRUCTURE USING SHALLOW TRENCH ISOLATION.

Y. Niitsu*, S. Taguchi, K. Shibata, H. Fuji, Y. Shimamune, H. Iwai, K. Kanzaki

*此作品的通信作者

研究成果: Conference article同行評審

7 引文 斯高帕斯(Scopus)

摘要

Using a shallow trench and a thin epitaxial layer, latchup-free CMOS has been realized. When the trench depth is 1. 4 mu m and the epitaxial layer thickness is 2 mu m, the latchup holding voltage, V//H , is higher than 13 V. The mechanism of V//H increase is discussed using an equivalent circuit that includes the reverse transistors of the parasitic bipolar transistors. The interruption of lateral current flow by the trench contributes to V//H increase. The results indicate that a trench only about 1 mu m deep would be adequate for achieving V//H higher than the supply voltage, i. e. , 5 V, and that the trench isolation process would become more reliable and easier.

原文English
頁(從 - 到)509-512
頁數4
期刊Technical Digest - International Electron Devices Meeting
DOIs
出版狀態Published - 1985

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