Using a shallow trench and a thin epitaxial layer, latchup-free CMOS has been realized. When the trench depth is 1. 4 mu m and the epitaxial layer thickness is 2 mu m, the latchup holding voltage, V//H , is higher than 13 V. The mechanism of V//H increase is discussed using an equivalent circuit that includes the reverse transistors of the parasitic bipolar transistors. The interruption of lateral current flow by the trench contributes to V//H increase. The results indicate that a trench only about 1 mu m deep would be adequate for achieving V//H higher than the supply voltage, i. e. , 5 V, and that the trench isolation process would become more reliable and easier.
|頁（從 - 到）||509-512|
|期刊||Technical Digest - International Electron Devices Meeting|
|出版狀態||Published - 1985|