Latch-up Risk in 5V-tolerant I/O Buffer Surrounded by NBL Isolation Ring with Low-Voltage Bias

For safe application of IC products, ensuring the integrity of CMOS integrated circuits (ICs) necessitates the verification of I/O pins through latch-up I-test that conforming to the standard of JEDEC JESD78F. The integration of high-voltage (HV) and low-voltage (LV) circuits within a single chip has been achieved in BCD technology. Typically, the LV circuits must be surrounded by an N-type buried layer (NBL) isolation ring to mitigate noise interference from the common p-substrate. However, in a mixed-voltage IC utilizing in 0.18-μm BCD technology, an unexpected parasitic latch-up path emerges from the 5V-tolerant I/O circuits to the NBL isolation ring. Such an unexpected parasitic latch-up path would fail the IC products to pass the requested latch-up I-test. Identifying such a latch-up risk has been practically verified in this study.