TY - GEN
T1 - LASER - Layout-aware Analog Synthesis Environment on Laker
AU - Liao, Yu Ching
AU - Chen, Yen Lung
AU - Cai, Xian Ting
AU - Liu, Chien-Nan
AU - Chen, Tai Chen
PY - 2013
Y1 - 2013
N2 - In modern technology, layout effects have more and more impacts on circuit performance. However, most of the existing analog automation tools consider the circuit sizing and layout generation in two separate steps, which often result in time-consuming sizing-layout iterations. In this paper, a layout-aware analog synthesis tool is presented to generate the required designs from specifications to layout through a user-friendly GUI. In order to provide a strong link between sizing and layout steps, a parasitic-aware circuit sizing flow is proposed based on a flexible layout template to prevent the performance from failing to meet the specifications after layout. Routability-aware analog placement is then performed with a simple routing algorithm to generate the corresponding layout with minimized cost. As demonstrated in the experimental results, this analog synthesis tool is able to generate the required circuits in seconds with high quality layouts and effectively guarantees the post-layout performance with less over-design.
AB - In modern technology, layout effects have more and more impacts on circuit performance. However, most of the existing analog automation tools consider the circuit sizing and layout generation in two separate steps, which often result in time-consuming sizing-layout iterations. In this paper, a layout-aware analog synthesis tool is presented to generate the required designs from specifications to layout through a user-friendly GUI. In order to provide a strong link between sizing and layout steps, a parasitic-aware circuit sizing flow is proposed based on a flexible layout template to prevent the performance from failing to meet the specifications after layout. Routability-aware analog placement is then performed with a simple routing algorithm to generate the corresponding layout with minimized cost. As demonstrated in the experimental results, this analog synthesis tool is able to generate the required circuits in seconds with high quality layouts and effectively guarantees the post-layout performance with less over-design.
KW - analog
KW - parasitic-aware sizing
KW - routability-aware placement
KW - synthesis
UR - http://www.scopus.com/inward/record.url?scp=84878211987&partnerID=8YFLogxK
U2 - 10.1145/2483028.2483071
DO - 10.1145/2483028.2483071
M3 - Conference contribution
AN - SCOPUS:84878211987
SN - 9781450319027
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 107
EP - 112
BT - GLSVLSI 2013 - Proceedings of the ACM International Conference of the Great Lakes Symposium on VLSI
T2 - 23rd ACM International Conference of the Great Lakes Symposium on VLSI, GLSVLSI 2013
Y2 - 2 May 2013 through 3 May 2013
ER -