LASER - Layout-aware Analog Synthesis Environment on Laker

Yu Ching Liao, Yen Lung Chen, Xian Ting Cai, Chien-Nan Liu, Tai Chen Chen

研究成果: Conference contribution同行評審

16 引文 斯高帕斯(Scopus)

摘要

In modern technology, layout effects have more and more impacts on circuit performance. However, most of the existing analog automation tools consider the circuit sizing and layout generation in two separate steps, which often result in time-consuming sizing-layout iterations. In this paper, a layout-aware analog synthesis tool is presented to generate the required designs from specifications to layout through a user-friendly GUI. In order to provide a strong link between sizing and layout steps, a parasitic-aware circuit sizing flow is proposed based on a flexible layout template to prevent the performance from failing to meet the specifications after layout. Routability-aware analog placement is then performed with a simple routing algorithm to generate the corresponding layout with minimized cost. As demonstrated in the experimental results, this analog synthesis tool is able to generate the required circuits in seconds with high quality layouts and effectively guarantees the post-layout performance with less over-design.

原文English
主出版物標題GLSVLSI 2013 - Proceedings of the ACM International Conference of the Great Lakes Symposium on VLSI
頁面107-112
頁數6
DOIs
出版狀態Published - 2013
事件23rd ACM International Conference of the Great Lakes Symposium on VLSI, GLSVLSI 2013 - Paris, 法國
持續時間: 2 5月 20133 5月 2013

出版系列

名字Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference23rd ACM International Conference of the Great Lakes Symposium on VLSI, GLSVLSI 2013
國家/地區法國
城市Paris
期間2/05/133/05/13

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