Junctionless Poly-Si Nanowire Transistors with Low-Temperature Trimming Process for Monolithic 3-D IC Application

Jer Yi Lin, Po Yi Kuo*, Ko Li Lin, Chun Chieh Chin, Tien-Sheng Chao

*此作品的通信作者

研究成果: Article同行評審

18 引文 斯高帕斯(Scopus)

摘要

In this paper, the junctionless (JL) ultrathin polycrystalline-Si (poly-Si) nanowire (NW) transistors with gate-all-around configuration and raised source/drain were successfully fabricated by a low-temperature trimming process. The 140 °C-heated phosphoric acid (HPA) was adopted for trimming the channel dimension, which exhibits a near roughness degradation-free etching and excellent trimming uniformity. As the HPA immersing time increased, the channel dimension was thinned and narrowed, resulting in the greater electrostatic integrity. Therefore, the steep subthreshold swing 75 mV/decade, low drain-induced barrier lowering ∼33 mV/V, and high on/off currents ratio (ION/IOFF) ∼ 7 × 106 can be achieved. These superior characteristics of low-temperature JL poly-Si NW transistors are promising candidates for the low thermal budget monolithic 3-D ICs and the system on panel applications in the future.

原文English
文章編號7676340
頁(從 - 到)4998-5003
頁數6
期刊IEEE Transactions on Electron Devices
63
發行號12
DOIs
出版狀態Published - 12月 2016

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