Junctionless Nanosheet (3 nm) Poly-Si TFT: Electrical Characteristics and Superior Positive Gate Bias Stress Reliability

Jer Yi Lin, Malkundi Puttaveerappa Vijay Kumar, Tien-Sheng Chao*

*此作品的通信作者

研究成果: Article同行評審

17 引文 斯高帕斯(Scopus)

摘要

In this letter, a junctionless (JL) poly-Si thin-film transistor (TFT) with a 3-nm-thick nanosheet channel is successfully fabricated using the low-temperature atomic level etching process. An inversion-mode (IM) TFT is also prepared for performance comparison and reliability investigation of positive gate bias stress (PGBS). In comparison with the IM-TFT, the JL-TFT exhibits superior PGBS reliability. The origin of the difference in degradation rates between the JL and IM-TFTs is ascribed to the different transport mechanisms and different gate dielectric fields under the same gate over-drive stress. Nanosheet JL-TFTs with a 3-nm channel thickness show excellent S.S (69 mV/decade) and extremely low off-current (1.93 fA). Results indicate that it is a promising candidate for low-power 3-D integrated circuits.

原文English
文章編號8126800
頁(從 - 到)8-11
頁數4
期刊IEEE Electron Device Letters
39
發行號1
DOIs
出版狀態Published - 1 1月 2018

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