Jitter compensation technique for continuous-time sigma-delta modulator

Zong Yi Chen, Chung-Chih Hung

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

This paper proposes a new compensation technique to reduce the clock jitter effects for the continuous-time sigma-delta (CT-ΣΔ) modulator by using divided-by-n (D-N) feedback DAC waveform. There are two types of clock jitter: independent clock jitter (random jitter) and accumulated clock jitter (deterministic jitter). This technique provides a useful approach to solve one of the critical non-idealities, independent clock jitter, in the CT-ΣΔ modulator without increasing the speed requirement of the modulator as well as the complexity of system and circuit design. This technique can be implemented with the proposed DLL-based clock generator. The results prove the effectiveness of this new compensation technique for independent clock jitter.

原文English
主出版物標題2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
發行者Institute of Electrical and Electronics Engineers Inc.
頁面423-426
頁數4
版本February
ISBN(電子)9781479952304
DOIs
出版狀態Published - 5 2月 2015
事件2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 - Ishigaki Island, Okinawa, Japan
持續時間: 17 11月 201420 11月 2014

出版系列

名字IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
號碼February
2015-February

Conference

Conference2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
國家/地區Japan
城市Ishigaki Island, Okinawa
期間17/11/1420/11/14

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