JAIP-MP: A four-core Java application processor for embedded systems

Chun-Jen Tsai*, Tsung Han Wu, Hung Cheng Su, Cheng Yang Chen

*此作品的通信作者

研究成果: Conference article同行評審

摘要

In this chapter, we present a four-core Java application processor, JAIP-MP. In addition to supporting multi-core coherent data accesses to shared memory, each processor core in JAIP-MP is a hardwired Java core that is capable of dynamic class loading, two-fold bytecode execution, object-oriented dynamic resolution, method/object caching, Java exception handling, preemptive multithreading, and memory management. Most of the essential OS kernel functions are implemented in hardware. In particular, the preemptive multi-threading performance is much higher than that of a software-based VM running on a traditional OS kernel such as Linux. Currently, single-cycle context switching with a time quantum as small as 20 μs can be achieved by each core. More importantly, the Java language model itself makes it possible to maintain binary portability of application software regardless of the hardwired OS kernel component. In summary, JAIP-MP could be used to study the potential benefits of OS kernel implementation in hardware.

原文English
頁(從 - 到)170-192
頁數23
期刊IFIP Advances in Information and Communication Technology
483
DOIs
出版狀態Published - 2016
事件23rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015 - Daejeon, Korea, Republic of
持續時間: 5 10月 20157 10月 2015

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