TY - GEN
T1 - JAIP-MP
T2 - 23rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015
AU - Tsai, Chun-Jen
AU - Wu, Tsung Han
AU - Su, Hung Cheng
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/10/30
Y1 - 2015/10/30
N2 - In this paper, we present the design of a four-core Java application processor, JAIP-MP. Each processor core in JAIP-MP is a hardwired Java core that supports dynamic class loading, two-fold bytecode execution, object-oriented dynamic resolution, method and object caching, Java exception handling, and temporal multithreading. For JAIP-MP, a global load-balancing task manager is used to evenly distribute Java threads among the local task queues of every processor cores. In addition, a data coherence controller is designed to enforce coherence across all data caches and to perform synchronization operations among Java threads of all processor cores. Since thread management and synchronization mechanisms are completely implemented in hardware, the single-core multi-tasking performance of JAIP-MP is much higher than that of a software-based VM running on a traditional OS kernel such as Linux. For execution of multithreading applications, the speedup of a four-core JAIP-MP system can be up to 3.69 times faster than a single-core JAIP system, tested using the JemBench parallel benchmark programs.
AB - In this paper, we present the design of a four-core Java application processor, JAIP-MP. Each processor core in JAIP-MP is a hardwired Java core that supports dynamic class loading, two-fold bytecode execution, object-oriented dynamic resolution, method and object caching, Java exception handling, and temporal multithreading. For JAIP-MP, a global load-balancing task manager is used to evenly distribute Java threads among the local task queues of every processor cores. In addition, a data coherence controller is designed to enforce coherence across all data caches and to perform synchronization operations among Java threads of all processor cores. Since thread management and synchronization mechanisms are completely implemented in hardware, the single-core multi-tasking performance of JAIP-MP is much higher than that of a software-based VM running on a traditional OS kernel such as Linux. For execution of multithreading applications, the speedup of a four-core JAIP-MP system can be up to 3.69 times faster than a single-core JAIP system, tested using the JemBench parallel benchmark programs.
KW - Java processor
KW - cache coherence
KW - embedded SoC
KW - hardwired multi-threading
KW - multi-core
UR - http://www.scopus.com/inward/record.url?scp=84960102080&partnerID=8YFLogxK
U2 - 10.1109/VLSI-SoC.2015.7314414
DO - 10.1109/VLSI-SoC.2015.7314414
M3 - Conference contribution
AN - SCOPUS:84960102080
T3 - IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
SP - 189
EP - 194
BT - 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015
PB - IEEE Computer Society
Y2 - 5 October 2015 through 7 October 2015
ER -