Investigation on selectively etched SiGe and Si surface for Gate-All-Around CMOS devices fabrication

Wei Yuan Chang; Chun Lin Chu; Guang Li Luo; Yi Shuo Huang; Chun Hsiung Lin; Po Jung Sung; Yao Jen Lee; Shih Hong Chen; Bo Yuan Chen; Wen Fa Wu; Wen Kuan Yeh

doi:10.1109/VLSI-TSA54299.2022.9770996

Investigation on selectively etched SiGe and Si surface for Gate-All-Around CMOS devices fabrication

Wei Yuan Chang, Chun Lin Chu, Guang Li Luo^*, Yi Shuo Huang, Chun Hsiung Lin, Po Jung Sung, Yao Jen Lee, Shih Hong Chen, Bo Yuan Chen, Wen Fa Wu^*, Wen Kuan Yeh

^*此作品的通信作者

國際半導體產業學院

研究成果: Conference contribution › 同行評審

5 引文斯高帕斯（Scopus）

摘要

The Si0.8Ge0.2 GAA-FET were successfully fabricated with Si GAA-FET using the same epi-layers and HKMG process for CMOS device fabrication. This study approached two selective etching processes and investigated both etched surfaces to obtain the multi-bridge channels (MBCs) for advanced SiGe p-FET and Si n-FET. The etched Si layers used in GAAFETs showed a practical on/off ratio with a subthreshold slope (SS) of 90 mV/decade. On the other hand, the etched surface of the advanced SiGe layers showed noticeable interface defects, and it was optimized by using PMA 800oC/5min.

原文	English
主出版物標題	2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9781665409230
DOIs	https://doi.org/10.1109/VLSI-TSA54299.2022.9770996
出版狀態	Published - 2022
事件	2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022 - Hsinchu, 台灣持續時間: 18 4月 2022 → 21 4月 2022

出版系列

名字	2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022

Conference

Conference	2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022
國家/地區	台灣
城市	Hsinchu
期間	18/04/22 → 21/04/22

存取文件

10.1109/VLSI-TSA54299.2022.9770996

其它文件與鏈接

Link to publication in Scopus

引用此

Chang, W. Y., Chu, C. L., Luo, G. L., Huang, Y. S., Lin, C. H., Sung, P. J., Lee, Y. J., Chen, S. H., Chen, B. Y., Wu, W. F., & Yeh, W. K. (2022). Investigation on selectively etched SiGe and Si surface for Gate-All-Around CMOS devices fabrication. 於 2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022 (2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA54299.2022.9770996

Chang, Wei Yuan ; Chu, Chun Lin ; Luo, Guang Li 等. / Investigation on selectively etched SiGe and Si surface for Gate-All-Around CMOS devices fabrication. 2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022. Institute of Electrical and Electronics Engineers Inc., 2022. (2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022).

@inproceedings{fa17b1aadcfa4975a9248ed9b117279d,

title = "Investigation on selectively etched SiGe and Si surface for Gate-All-Around CMOS devices fabrication",

abstract = "The Si0.8Ge0.2 GAA-FET were successfully fabricated with Si GAA-FET using the same epi-layers and HKMG process for CMOS device fabrication. This study approached two selective etching processes and investigated both etched surfaces to obtain the multi-bridge channels (MBCs) for advanced SiGe p-FET and Si n-FET. The etched Si layers used in GAAFETs showed a practical on/off ratio with a subthreshold slope (SS) of 90 mV/decade. On the other hand, the etched surface of the advanced SiGe layers showed noticeable interface defects, and it was optimized by using PMA 800oC/5min.",

author = "Chang, {Wei Yuan} and Chu, {Chun Lin} and Luo, {Guang Li} and Huang, {Yi Shuo} and Lin, {Chun Hsiung} and Sung, {Po Jung} and Lee, {Yao Jen} and Chen, {Shih Hong} and Chen, {Bo Yuan} and Wu, {Wen Fa} and Yeh, {Wen Kuan}",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022 ; Conference date: 18-04-2022 Through 21-04-2022",

year = "2022",

doi = "10.1109/VLSI-TSA54299.2022.9770996",

language = "English",

series = "2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022",

address = "美國",

}

Chang, WY, Chu, CL, Luo, GL, Huang, YS, Lin, CH, Sung, PJ, Lee, YJ, Chen, SH, Chen, BY, Wu, WF & Yeh, WK 2022, Investigation on selectively etched SiGe and Si surface for Gate-All-Around CMOS devices fabrication. 於 2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022. 2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022, Institute of Electrical and Electronics Engineers Inc., 2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022, Hsinchu, 台灣, 18/04/22. https://doi.org/10.1109/VLSI-TSA54299.2022.9770996

Investigation on selectively etched SiGe and Si surface for Gate-All-Around CMOS devices fabrication. / Chang, Wei Yuan; Chu, Chun Lin; Luo, Guang Li 等.
2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022. Institute of Electrical and Electronics Engineers Inc., 2022. (2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Investigation on selectively etched SiGe and Si surface for Gate-All-Around CMOS devices fabrication

AU - Chang, Wei Yuan

AU - Chu, Chun Lin

AU - Luo, Guang Li

AU - Huang, Yi Shuo

AU - Lin, Chun Hsiung

AU - Sung, Po Jung

AU - Lee, Yao Jen

AU - Chen, Shih Hong

AU - Chen, Bo Yuan

AU - Wu, Wen Fa

AU - Yeh, Wen Kuan

PY - 2022

Y1 - 2022

N2 - The Si0.8Ge0.2 GAA-FET were successfully fabricated with Si GAA-FET using the same epi-layers and HKMG process for CMOS device fabrication. This study approached two selective etching processes and investigated both etched surfaces to obtain the multi-bridge channels (MBCs) for advanced SiGe p-FET and Si n-FET. The etched Si layers used in GAAFETs showed a practical on/off ratio with a subthreshold slope (SS) of 90 mV/decade. On the other hand, the etched surface of the advanced SiGe layers showed noticeable interface defects, and it was optimized by using PMA 800oC/5min.

AB - The Si0.8Ge0.2 GAA-FET were successfully fabricated with Si GAA-FET using the same epi-layers and HKMG process for CMOS device fabrication. This study approached two selective etching processes and investigated both etched surfaces to obtain the multi-bridge channels (MBCs) for advanced SiGe p-FET and Si n-FET. The etched Si layers used in GAAFETs showed a practical on/off ratio with a subthreshold slope (SS) of 90 mV/decade. On the other hand, the etched surface of the advanced SiGe layers showed noticeable interface defects, and it was optimized by using PMA 800oC/5min.

UR - http://www.scopus.com/inward/record.url?scp=85130509560&partnerID=8YFLogxK

U2 - 10.1109/VLSI-TSA54299.2022.9770996

DO - 10.1109/VLSI-TSA54299.2022.9770996

M3 - Conference contribution

AN - SCOPUS:85130509560

T3 - 2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022

BT - 2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022

Y2 - 18 April 2022 through 21 April 2022

ER -

Chang WY, Chu CL, Luo GL, Huang YS, Lin CH, Sung PJ 等. Investigation on selectively etched SiGe and Si surface for Gate-All-Around CMOS devices fabrication. 於 2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022. Institute of Electrical and Electronics Engineers Inc. 2022. (2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022). doi: 10.1109/VLSI-TSA54299.2022.9770996

Investigation on selectively etched SiGe and Si surface for Gate-All-Around CMOS devices fabrication

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