Investigation on safe operating area and ESD robustness in a 60-V BCD process with different deep P-Well test structures

Keyphrases

• Electrostatic Discharge 100%
• BCD Process 100%
• Safe Operating Space 100%
• Well Testing 100%
• Deep P-well 100%
• Well Structure 75%
• High-voltage MOSFET 75%
• Power IC 50%
• Operating Conditions 25%
• MOSFET 25%
• Silicon Area 25%
• Electrostatic Discharge (ESD) Protection 25%
• Reliability Issues 25%
• Power MOSFET 25%
• Silicon chip 25%
• Self-protection 25%
• Protection Device 25%
• High-voltage Device 25%
• High Operating Voltage 25%
• Reduced Surface Field (RESURF) 25%

Engineering

• Metal-Oxide-Semiconductor Field-Effect Transistor 100%
• Electrostatic Discharge 100%
• Test Structure 100%
• Operating Area 100%
• Experimental Result 20%
• Operating Voltage 20%
• Reliability Issue 20%
• Protection Device 20%
• Surface Field 20%
• Service-Oriented Architecture 20%