TY - GEN
T1 - Investigation on RF characteristics of stacked P-I-N polysilicon diodes for ESD protection design in 0.18-μm CMOS technology
AU - Shiu, Yu Da
AU - Chuang, Che Hao
AU - Ker, Ming-Dou
PY - 2006
Y1 - 2006
N2 - An ESD protection design by using the stacked P-I-N polysilicon diodes for CMOS RF integrated circuits is proposed to reduce the input capacitance and to avoid the noise coupling from the common substrate. In this paper, the dc I-V characteristics, RF S-parameters, and ESD robustness of the stacked P-I-N polysilicon diodes are investigated in a 0.18-μm salicided CMOS process. This polysilicon diode with small parasitic capacitance and high ESD robustness is fully process compatible to general CMOS process without extra process modification.
AB - An ESD protection design by using the stacked P-I-N polysilicon diodes for CMOS RF integrated circuits is proposed to reduce the input capacitance and to avoid the noise coupling from the common substrate. In this paper, the dc I-V characteristics, RF S-parameters, and ESD robustness of the stacked P-I-N polysilicon diodes are investigated in a 0.18-μm salicided CMOS process. This polysilicon diode with small parasitic capacitance and high ESD robustness is fully process compatible to general CMOS process without extra process modification.
UR - http://www.scopus.com/inward/record.url?scp=33847665795&partnerID=8YFLogxK
U2 - 10.1109/VTSA.2006.251064
DO - 10.1109/VTSA.2006.251064
M3 - Conference contribution
AN - SCOPUS:33847665795
SN - 142440181X
SN - 9781424401819
T3 - International Symposium on VLSI Technology, Systems, and Applications, Proceedings
SP - 56
EP - 57
BT - 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers
T2 - 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA
Y2 - 24 April 2006 through 26 April 2006
ER -