Investigation on Latch-Up Path between I/O PMOS and Core PMOS in a 0.18-μm CMOS Process

Chun Cheng Chen, Ming-Dou Ker

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

This work studied the latch-up path between two PMOS devices powered by different supply voltages in a 0.18μm CMOS process. In IC field applications, such a non-typical latchup path between two PMOS devices was ever fired to cause unrecoverable failures. Through the silicon test chip, the latch-up path between I/O PMOS and core PMOS was investigated in details. The measurement results from the silicon chip with split test structures can be used to investigate the design rules on anode-to-cathode spacing and guard ring placement to prevent such PMOS-to-PMOS latch-up issue. In chip layout of IC products, the PMOS devices in different power domains shall be carefully checked to prevent the occurrence of such unexpected latch-up path.

原文English
主出版物標題2019 IEEE International Reliability Physics Symposium, IRPS 2019
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781538695043
DOIs
出版狀態Published - 22 五月 2019
事件2019 IEEE International Reliability Physics Symposium, IRPS 2019 - Monterey, United States
持續時間: 31 三月 20194 四月 2019

出版系列

名字IEEE International Reliability Physics Symposium Proceedings
2019-March
ISSN(列印)1541-7026

Conference

Conference2019 IEEE International Reliability Physics Symposium, IRPS 2019
國家/地區United States
城市Monterey
期間31/03/194/04/19

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