Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-μm partially-depleted SOI salicide CMOS technology

Ming-Dou Ker; K. K. Hong; T. Y. Chen; H. Tang; S. C. Huang; S. S. Chen; C. T. Huang; M. C. Wang; Y. T. Loh

doi:10.1109/VTSA.2001.934478

Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-μm partially-depleted SOI salicide CMOS technology

Ming-Dou Ker^*, K. K. Hong, T. Y. Chen, H. Tang, S. C. Huang, S. S. Chen, C. T. Huang, M. C. Wang, Y. T. Loh

^*此作品的通信作者

研究成果: Paper › 同行評審

1 引文斯高帕斯（Scopus）

摘要

Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-μm partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process.

原文	English
頁面	41-44
頁數	4
DOIs	https://doi.org/10.1109/VTSA.2001.934478
出版狀態	Published - 18 4月 2001
事件	2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings - Hsinchu, Taiwan 持續時間: 18 4月 2001 → 20 4月 2001

Conference

Conference	2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings
國家/地區	Taiwan
城市	Hsinchu
期間	18/04/01 → 20/04/01

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10.1109/VTSA.2001.934478

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Ker, M-D., Hong, K. K., Chen, T. Y., Tang, H., Huang, S. C., Chen, S. S., Huang, C. T., Wang, M. C., & Loh, Y. T. (2001). Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-μm partially-depleted SOI salicide CMOS technology. 41-44. 論文發表於 2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings, Hsinchu, Taiwan. https://doi.org/10.1109/VTSA.2001.934478

@conference{ce9d50ce2d3c47c4b59097792426820f,

title = "Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-μm partially-depleted SOI salicide CMOS technology",

abstract = "Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-μm partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process.",

author = "Ming-Dou Ker and Hong, {K. K.} and Chen, {T. Y.} and H. Tang and Huang, {S. C.} and Chen, {S. S.} and Huang, {C. T.} and Wang, {M. C.} and Loh, {Y. T.}",

year = "2001",

month = apr,

day = "18",

doi = "10.1109/VTSA.2001.934478",

language = "English",

pages = "41--44",

note = "2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings ; Conference date: 18-04-2001 Through 20-04-2001",

}

Ker, M-D, Hong, KK, Chen, TY, Tang, H, Huang, SC, Chen, SS, Huang, CT, Wang, MC & Loh, YT 2001, 'Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-μm partially-depleted SOI salicide CMOS technology', 論文發表於 2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings, Hsinchu, Taiwan, 18/04/01 - 20/04/01 頁 41-44. https://doi.org/10.1109/VTSA.2001.934478

TY - CONF

T1 - Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-μm partially-depleted SOI salicide CMOS technology

AU - Ker, Ming-Dou

AU - Hong, K. K.

AU - Chen, T. Y.

AU - Tang, H.

AU - Huang, S. C.

AU - Chen, S. S.

AU - Huang, C. T.

AU - Wang, M. C.

AU - Loh, Y. T.

PY - 2001/4/18

Y1 - 2001/4/18

N2 - Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-μm partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process.

AB - Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-μm partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process.

UR - http://www.scopus.com/inward/record.url?scp=0034854842&partnerID=8YFLogxK

U2 - 10.1109/VTSA.2001.934478

DO - 10.1109/VTSA.2001.934478

M3 - Paper

AN - SCOPUS:0034854842

SP - 41

EP - 44

T2 - 2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Y2 - 18 April 2001 through 20 April 2001

ER -

Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-μm partially-depleted SOI salicide CMOS technology

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