Investigation of Vth Distribution Tails of Ground-Select-Line Cells and Edge Dummy Cells in a 3-D NAND Flash Memory

You Liang Chou, Tahui Wang, C. C. Cheng, C. C. Lu, G. W. Wu, S. H. Ku, Wen Chang, Wen Jer Tsai, Tao Cheng Lu, Kuang Chao Chen, Chih Yuan Lu

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

The threshold voltage ( {V} th) distributions of ground-select-line (GSL) cells and edge dummy (DMY0) cells in a 3-D NAND flash memory are investigated. We characterize the {V} th distributions in 3-D NAND flash samples with different fabrication processes and bitline voltages. Large DMY0 and GSL {V} th distribution tails are observed in certain fabrication process and operation voltage conditions. The DMY0 {V} th tail is attributed to a random distribution of grain boundary (GB) traps in a poly-silicon channel between GSL and DMY0. The GSL {V} th tail is affected by ion implant energy in an epitaxial silicon layer underneath a GSL. A 3-D TCAD simulation is performed to study the effects of a GB trap position and a bitline voltage on the {V} th distribution of DMY0. The influence of an implant dose profile in the epitaxial silicon on the GSL {V} th distribution is also analyzed by 3-D simulation. The GSL and the DMY0 {V} th distributions can be significantly improved by optimizing a fabrication process and choosing an appropriate bitline voltage.

原文English
文章編號9380572
頁(從 - 到)2260 - 2264
頁數5
期刊IEEE Transactions on Electron Devices
68
發行號5
DOIs
出版狀態Published - 5月 2021

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