Investigation of Unexpected Latchup Path between HV-LDMOS and LV-CMOS in a 0.25- μm 60-V/5-V BCD Technology

Chia Tsen Dai*, Ming-Dou Ker

*此作品的通信作者

研究成果: Article同行評審

5 引文 斯高帕斯(Scopus)

摘要

The latchup path which may potentially exist at the interface between high-voltage (HV) and low-voltage (LV) circuits in a HV bipolar-CMOS-DMOS (BCD) technology is investigated in this brief. Owing to multiple well structures used to realize the HV device in the BCD process, the expected latchup path in the test structure was hardly triggered. However, a parasitic silicon-controlled rectifier path featuring a very low holding voltage is found in the experimental silicon chip. Such a parasitic path is first reported in the literature. It may influence the electrostatic discharge robustness of CMOS IC products with the HV and LV circuits integrated together. Thus, the layout rules at the HV and LV interface should be carefully defined to avoid the occurrence of an unexpected parasitic path.

原文English
文章編號7967689
頁(從 - 到)3519-3523
頁數5
期刊IEEE Transactions on Electron Devices
64
發行號8
DOIs
出版狀態Published - 1 八月 2017

指紋

深入研究「Investigation of Unexpected Latchup Path between HV-LDMOS and LV-CMOS in a 0.25- μm 60-V/5-V BCD Technology」主題。共同形成了獨特的指紋。

引用此