@inproceedings{d2ca1fabf5124ce5a39642cee6362161,
title = "Investigation of Interlayer Surface Roughness induced Variation in Scaled 2D Ferroelectric-FET Nonvolatile Memories",
abstract = "This work investigates the interfacial-layer (IL) surface roughness induced random variation in scaled 2D FeFET NVMs with the aid of TCAD atomistic simulations. Our study indicates that the IL surface roughness variation may significantly impact the FeFET NVM, and the variability in memory window (MW) increases as the gate length is scaled down. We have also compared the IL surface roughness induced variation for 2D FeFETs and Si FeFETs. Besides, we have demonstrated that using high-k spacer design can mitigate the IL surface roughness induced variation in addition to raising the MW. The impact of high-k spacers increases with the downscaling of gate length.",
author = "Chang, {Lung En} and Liu, {You Sheng} and Pin Su",
note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022 ; Conference date: 11-06-2022 Through 12-06-2022",
year = "2022",
doi = "10.1109/SNW56633.2022.9889038",
language = "English",
series = "2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022",
address = "United States",
}