This work investigates the interfacial-layer (IL) surface roughness induced random variation in scaled 2D FeFET NVMs with the aid of TCAD atomistic simulations. Our study indicates that the IL surface roughness variation may significantly impact the FeFET NVM, and the variability in memory window (MW) increases as the gate length is scaled down. We have also compared the IL surface roughness induced variation for 2D FeFETs and Si FeFETs. Besides, we have demonstrated that using high-k spacer design can mitigate the IL surface roughness induced variation in addition to raising the MW. The impact of high-k spacers increases with the downscaling of gate length.