Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs

Chen Wei Lin, Chia-Tso Chao, Chih Chieh Hsu

研究成果: Conference contribution同行評審

11 引文 斯高帕斯(Scopus)

摘要

When CMOS technologies enter nanometer scale, FinFET has become one of the most promising devices because of the superior electrical characteristics. Nonetheless, due to the scaling of dielectric thickness and the occurring of line-edge roughness, FinFETs may suffer the gate oxide short. Gate oxide short is a defect that has been widely discussed in planar bulk MOSFETs. But for FinFETs, the defect characteristics have not been studied yet. In this paper, we investigate the fault behaviors of the gate oxide short in FinFETs. The investigation includes both tied-gate and independent-gate FinFETs. Based on the TCAD mixed-mode simulations, we discover that the gate oxide short in the two types of FinFETs causes different fault behaviors from each other. Compared to planar bulk MOSFETs, the fault behaviors are even more complex. In addition to the discussion at device level, we also discuss the corresponding SRAM testing. For detecting gate oxide short in FinFET SRAMs, we propose two new test methods. By using TCAD transient simulations, we prove the two methods' test efficacy of detecting the gate oxide shorts uncovered by traditional test methods.

原文English
主出版物標題Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013
DOIs
出版狀態Published - 14 8月 2013
事件2013 IEEE 31st VLSI Test Symposium, VTS 2013 - Berkeley, CA, United States
持續時間: 29 4月 20131 5月 2013

出版系列

名字Proceedings of the IEEE VLSI Test Symposium

Conference

Conference2013 IEEE 31st VLSI Test Symposium, VTS 2013
國家/地區United States
城市Berkeley, CA
期間29/04/131/05/13

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