Investigation of ESD protection devices for SiC-based monolithic integrated circuits

ESD characterization of on-chip ESD protection devices, including the gate-grounded NMOS (GGNMOS), the gate-VDD PMOS (GDPMOS), the N+/PW diode, and the P+/NW diode was investigated. With respect to GGNMOS and GDPMOS, ESD robustness was unrelated to the number of fingers under the breakdown mode. On the contrary, under the forward mode, ESD robustness can be effectively enhanced by increasing the number of fingers. Similar results were observed on the N+/PW and the P+/NW diodes. Under the breakdown mode, ESD robustness was not related to the junction perimeter of the diode. Under the forward mode, ESD robustness can be effectively enhanced by increasing the junction perimeter. By comparing the figure of merit (FoM) among these four devices, the FoM of diode is higher than that of MOS-based ESD devices. Moreover, the concept of whole-chip ESD protection with power-rail ESD clamp circuit was recommended to guarantee the sufficient ESD robustness of SiC-based integrated circuits.