Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETs

Vita Pi Ho Hu, Pin Su, Ching Te Chuang

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

This paper investigates the impacts of negative and positive bias temperature instabilities (NBTI and PBTI) on the stability and performance of ultra-thin-body (UTB) GeOI 6T SRAM cells integrated in monolithic 3D scheme with interlayer coupling. Various bitcell layouts with different gate alignments of transistors from distinct layers are investigated. The worst case stress scenarios for read and write operations are analyzed. The optimized monolithic 3D UTB GeOI SRAM with the pulldown NFET tier stacked over the pull-up PFET tier and under forward PFET back-gate bias shows improvements in read stability and cell read-access time compared with the 2D UTB GeOI SRAM. Monolithic 3D UTB GeOI SRAM with high threshold voltage (Vth) design can enhance the improvements in stability and performance over 2D SRAM. Moreover, the optimized monolithic 3D UTB GeOI SRAM can mitigate the temporal degradations in stability and performance due to BTI stress because the BTI induced Vth degradations can be suppressed by interlayer coupling in monolithic 3D scheme.

原文English
主出版物標題ISCAS 2016 - IEEE International Symposium on Circuits and Systems
發行者Institute of Electrical and Electronics Engineers Inc.
頁面2106-2109
頁數4
ISBN(電子)9781479953400
DOIs
出版狀態Published - 29 7月 2016
事件2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, 加拿大
持續時間: 22 5月 201625 5月 2016

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
2016-July
ISSN(列印)0271-4310

Conference

Conference2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
國家/地區加拿大
城市Montreal
期間22/05/1625/05/16

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