Intrinsic Difference between 2-D Negative-Capacitance FETs with Semiconductor-on-Insulator and Double-Gate Structures

Wei Xiang You, Pin Su*

*此作品的通信作者

研究成果: Article同行評審

16 引文 斯高帕斯(Scopus)

摘要

With the aid of an analytical and general model, this paper investigates the intrinsic difference in the negative-capacitance (NC) effect and design space between semiconductor-on-insulator (SOI) and double-gate (DG) metal-ferroelectric-insulator-semiconductor-type NC field-effect transistors (NCFETs) with a 2-D semiconducting transition-metal-dichalcogenide channel (2-D NCFET). By examining the distributions of internal charge, voltage gain, and capacitance matching over the whole bias range, the intrinsic difference in NC effects between these two topologies is pointed out and explained. Our study indicates that for an intrinsic DG 2-D NCFET, it is difficult to achieve sub-2.3 kT/q average subthreshold swing (SS). By contrast, the bias-dependent subthreshold internal charge and larger curvature of ferroelectric capacitance due to the independent backgate in the SOI 2-D NCFET enable larger design space and sub-2.3 kT/q average SS, making it more suitable for low-power applications.

原文English
文章編號8454292
頁(從 - 到)4196-4201
頁數6
期刊IEEE Transactions on Electron Devices
65
發行號10
DOIs
出版狀態Published - 1 10月 2018

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