Intra-field gate CD variability and its impact on circuit performance

Michael Orshansky*, Linda Milor, Ly Nguyen, Gene Hill, Yeng Peng, Chen-Ming Hu


研究成果: Conference article同行評審

6 引文 斯高帕斯(Scopus)


Statistical analysis of an advanced CMOS process reveals a significant systematic within-field variability of gate CD strongly dependent on the local layout patterns. We present a novel modeling methodology for accurate prediction of the effect of such CD variability on circuit performance that enables statistical design for increased performance and yield. We also propose a mask-level gate CD correction algorithm allowing significant reduction of overall variability and provide a model to evaluate the effectiveness of correction.

頁(從 - 到)479-482
期刊Technical Digest - International Electron Devices Meeting
出版狀態Published - 1 十二月 1999
事件1999 IEEE International Devices Meeting (IEDM) - Washington, DC, USA
持續時間: 5 十二月 19998 十二月 1999


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