TY - GEN
T1 - Interface discrete trap induced variability for negative capacitance FinFETs
AU - Lee, Ho Pei
AU - Tseng, Kuei Yang
AU - Su, Pin
PY - 2018/7/3
Y1 - 2018/7/3
N2 - To fulfill the future need of ultra-low-power applications such as Internet-of-Things (IoT) technologies [1], steep-slope transistors are indispensable. Negative capacitance FET (NCFET) is one of the most promising steep-slope devices because it may possess sub-kT/q swing and high on/off current ratio simultaneously [2]. For scaled devices especially under low voltage operation, statistical variation is one major concern. The random variation may stem from intrinsic variations and discrete interface charges [3], [4]. The impact of the interface charge can also be an indication of the bias temperature instability (BTI) responsible for the time-dependent transistor degradation [5]. The research related to the impact of interface traps on the NCFET is still lacking and merits investigation. In this work, through atomistic TCAD simulation, we investigate the interface discrete trap induced variability for negative capacitance FinFETs (NC-FinFETs).
AB - To fulfill the future need of ultra-low-power applications such as Internet-of-Things (IoT) technologies [1], steep-slope transistors are indispensable. Negative capacitance FET (NCFET) is one of the most promising steep-slope devices because it may possess sub-kT/q swing and high on/off current ratio simultaneously [2]. For scaled devices especially under low voltage operation, statistical variation is one major concern. The random variation may stem from intrinsic variations and discrete interface charges [3], [4]. The impact of the interface charge can also be an indication of the bias temperature instability (BTI) responsible for the time-dependent transistor degradation [5]. The research related to the impact of interface traps on the NCFET is still lacking and merits investigation. In this work, through atomistic TCAD simulation, we investigate the interface discrete trap induced variability for negative capacitance FinFETs (NC-FinFETs).
UR - http://www.scopus.com/inward/record.url?scp=85050474686&partnerID=8YFLogxK
U2 - 10.1109/VLSI-TSA.2018.8403836
DO - 10.1109/VLSI-TSA.2018.8403836
M3 - Conference contribution
AN - SCOPUS:85050474686
T3 - 2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018
SP - 1
EP - 2
BT - 2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018
Y2 - 16 April 2018 through 19 April 2018
ER -