The impact of new interconnect materials and various circuit design techniques on both performance and signal integrity in future high-speed CMOS is investigated. Specifically, this work examines the use of copper, low-k dielectrics, repeaters, driver sizing and novel design techniques with respect to crosstalk and delay in the 0.25 to 0.07 μm generations. We show crosstalk to be very important in scaled ULSI interconnects and steps such as reduced aspect ratios and asymmetric pitches should be used to ensure signal integrity.
|頁（從 - 到）||42-43|
|期刊||Digest of Technical Papers - Symposium on VLSI Technology|
|出版狀態||Published - 1 一月 1998|
|事件||Proceedings of the 1998 Symposium on VLSI Technology - Honolulu, HI, USA|
持續時間: 9 六月 1998 → 11 六月 1998