Interconnect scaling: Signal integrity and performance in future high-speed CMOS designs

Dennis Sylvester*, Chen-Ming Hu, O. Sam Nakagawa, Soo Young Oh

*此作品的通信作者

研究成果: Conference article同行評審

38 引文 斯高帕斯(Scopus)

摘要

The impact of new interconnect materials and various circuit design techniques on both performance and signal integrity in future high-speed CMOS is investigated. Specifically, this work examines the use of copper, low-k dielectrics, repeaters, driver sizing and novel design techniques with respect to crosstalk and delay in the 0.25 to 0.07 μm generations. We show crosstalk to be very important in scaled ULSI interconnects and steps such as reduced aspect ratios and asymmetric pitches should be used to ensure signal integrity.

原文English
頁(從 - 到)42-43
頁數2
期刊Digest of Technical Papers - Symposium on VLSI Technology
DOIs
出版狀態Published - 1 一月 1998
事件Proceedings of the 1998 Symposium on VLSI Technology - Honolulu, HI, USA
持續時間: 9 六月 199811 六月 1998

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