Integration of high-k gate stack systems into planar CMOS process flows

H. R. Huff, A. Agarwal, Y. Kim, L. Perrymore, D. Riley, J. Barnett, C. Sparks, M. Freiler, G. Gebara, B. Bowers, P. J. Chen, P. Lysaght, B. Nguyen, J. E. Lim, S. Lim, G. Bersuker, P. Zeitzoff, G. A. Brown, C. Young, B. ForanF. Shaapur, Tuo-Hung Hou, C. Lim, H. Alshareef, S. Borthakur, D. J. Derro, R. Bergmann, L. A. Larson, M. I. Gardner, J. Gutt, R. W. Murto, K. Torres, M. D. Jackson

研究成果: Conference contribution同行評審

19 引文 斯高帕斯(Scopus)

摘要

We review several gate stack fabrication issues critical for robust, commercially viable tools, including assessment of possible fab contamination due to the higher-k gate dielectrics and the role of subsequent thermal procedures during, for example, source/drain anneals (including the importance of the oxygen partial pressure) to ensure their compatibility with conventional planar polysilicon CMOS transistor fabrication processes.

原文English
主出版物標題Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001
發行者Institute of Electrical and Electronics Engineers Inc.
頁面2-11
頁數10
ISBN(電子)4891140216, 9784891140212
DOIs
出版狀態Published - 1 1月 2001
事件International Workshop on Gate Insulator, IWGI 2001 - Tokyo, Japan
持續時間: 1 11月 20012 11月 2001

出版系列

名字Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001

Conference

ConferenceInternational Workshop on Gate Insulator, IWGI 2001
國家/地區Japan
城市Tokyo
期間1/11/012/11/01

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