TY - GEN
T1 - Integration of energy-recycling logic and wireless power transfer for ultra-low-power implantables
AU - Lin, Hsin Tzu
AU - Wu, Yi Chung
AU - Hsieh, Ping Hsuan
AU - Yang, Chia Hsiang
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/9/25
Y1 - 2017/9/25
N2 - This paper presents an integration of energy-recycling logic circuits with a wireless power transfer receiving module for ultra-low-power applications, such as transcutaneous biomedical implantables. In the prototype design, one inductive coil implanted inside the body receives wireless power and supplies the following electronics. While part of the loading is composed of conventional CMOS logics, the rest is implemented with energy-recycling logic circuits. Energy-recycling logic and the associated adiabatic operation achieve excellent energy efficiency by transferring and recycling energy between digital logic blocks along with the signal propagation. The required AC supplies further lead to a natural integration with wireless power transfer and therefore obviate the need for a rectifier that contributes to substantial power loss. As a proof of concept, a finite-impulse-response filter is designed in 90-nm CMOS process. Simulation results show a 59.3% power reduction as compared to static CMOS counterpart.
AB - This paper presents an integration of energy-recycling logic circuits with a wireless power transfer receiving module for ultra-low-power applications, such as transcutaneous biomedical implantables. In the prototype design, one inductive coil implanted inside the body receives wireless power and supplies the following electronics. While part of the loading is composed of conventional CMOS logics, the rest is implemented with energy-recycling logic circuits. Energy-recycling logic and the associated adiabatic operation achieve excellent energy efficiency by transferring and recycling energy between digital logic blocks along with the signal propagation. The required AC supplies further lead to a natural integration with wireless power transfer and therefore obviate the need for a rectifier that contributes to substantial power loss. As a proof of concept, a finite-impulse-response filter is designed in 90-nm CMOS process. Simulation results show a 59.3% power reduction as compared to static CMOS counterpart.
UR - http://www.scopus.com/inward/record.url?scp=85032682429&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2017.8050378
DO - 10.1109/ISCAS.2017.8050378
M3 - Conference contribution
AN - SCOPUS:85032682429
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Y2 - 28 May 2017 through 31 May 2017
ER -